The present invention relates to semiconductor devices using silicon on insulator (SOI) substrate, and manufacturing methods of the semiconductor devices. More particularly, the invention relates to a technique effectively applied to a semiconductor device for controlling the potential of a substrate via a silicon layer, and a manufacturing method of the semiconductor device.
Semiconductor devices with the SOI substrate have currently been used as a semiconductor device that can reduce the generation of parasitic capacitance. The SOI substrate includes a buried oxide (BOX) film formed over a support substrate comprised of Si(silicon) with a high resistance, and a thin layer (silicon layer) containing Si(silicon) as a principal component over the BOX film. The formation of a metal oxide semiconductor field-effect transistor (MOSFET) over the SOI substrate can reduce the parasitic capacitance caused in a diffusion region formed in the silicon layer. It can be expected that the use of the SOI substrate for manufacturing the semiconductor device improves the integration density and operation speed of the semiconductor device and achieves the latch-up-free structure of the semiconductor device.
In the technique disclosed in Patent Document 1 (Japanese Unexamined Patent Publication No. Hei 9 (1997)-312401), an impurity-doped polysilicon layer is formed over an upper surface of a support substrate under a silicon oxide film (BOX film) included in an SOI substrate. The potential of the impurity-doped polysilicon layer is controlled to store charges in the polysilicon layer, which suppresses variations in threshold voltage of a MOSFET. The respective impurity-doped polysilicon layers under the n-channel MOSFET and the p-channel MOSFET are of an n-conduction type. The type of impurities to be introduced into the respective impurity-doped polysilicon layers under the MOSFETs is not changed between the n-channel MOSFET and the p-channel MOSFET.
A semiconductor device using an SOI substrate which is disclosed in Patent Document 2 (Japanese Unexamined Patent Publication No. 2001-177098) has a contact plug formed through a buried oxide (BOX) film and a silicon film over the BOX film and electrically coupled to a support substrate so as to control the potential of a support substrate under the BOX film included in an SOI substrate. In this technique, the potential of the support substrate is controlled through the contact plug to thereby control a threshold voltage, which can increase the speed of operation of a MOSFET, and can also reduce the power consumption and size of the MOSFET. The support substrate under the n-channel MOSFET has a p-type well region formed therein, and the support substrate under the p-channel MOSFET has an n-type well region formed therein. A contact plug for controlling the potential of the support substrate has a columnar shape. This patent document does not disclose that the contact plug extends along a main surface of the SOI substrate.
In an active state of the n-channel MOSFET, a voltage lower than a power-supply voltage is applied to the support substrate under the n-channel MOSFET. In a standby (off) state of the n-channel MOSFET, the power-supply voltage is applied to the support substrate. On the other hand, in an active state of the p-channel MOSFET, a voltage lower than a ground voltage is applied to the support substrate under the p-channel MOSFET. In a standby (off) state of the p-channel MOSFET, the ground voltage is applied to the support substrate. This patent document does not disclose that the potential of the support substrate is set to the same level as that of a gate electrode of the n-channel or p-channel MOSFET.
In the technique disclosed in Patent Document 3 (Japanese Unexamined Patent Publication No. 2007-115971) for controlling the potential of a support substrate under a gate electrode of a MOSFET, a semiconductor device formed over an SOI substrate has a contact plug electrically coupled to the support substrate, while penetrating a BOX film and a silicon film formed over the BOX film which are included in the SOI substrate. Through the contact plug, the potential of the support substrate can be controlled. A p-type well region is formed at the support substrate under the n-channel MOSFET, while an n-type well region is formed at the support substrate under the p-channel MOSFET. The contact plug for controlling the potential of the support substrate has a columnar shape. This patent document does not disclose that the contact plug extends along a main surface of the semiconductor substrate.
A substrate bias voltage is applied to the p-type well and the n-type well under the gate electrodes of the n-channel MOSFET and the p-channel MOSFET. A voltage between the gate and substrate is controlled by the substrate bias voltage. However, this patent document does not disclose that the potential of the gate electrode is set to the same level as a support potential of the substrate.